Terasic Technologies TR4 FPGA Development Kits
Terasic TR4 FPGA Development Kits provide the ideal hardware platform for system designs that demand high-performance, serial connectivity, and advanced memory interfacing. These boards and kits are based on the Altera Stratix® IV GX EP4SGX230 and EP4SGX530 FPGAs. Developed specifically to address the rapidly evolving requirements in many end markets for greater bandwidth, improved jitter performance, and lower power consumption, the TR4, and DE4 are powered by the Stratix IV GX devices and supported by industry-standard peripherals, connectors, and interfaces that offer a rich set of features suitable for a wide range of compute-intensive applications.
The advantages of the Stratix IV GX FPGA platform with embedded transceivers allow the Terasic TR4 to be fully compliant with version 2.0 of the PCI Express standard. This accelerates the mainstream development of PCI Express-based applications and enables customers to deploy designs for a broad range of high-speed connectivity applications.
The TR4 development kits are supported by multiple reference designs and six High-Speed Mezzanine Card (HSMC) connectors that allow scaling and customization with mezzanine daughter cards. For large-scale ASIC prototype development, multiple TR4s can be stacked together to create an easily customizable multi-FPGA system.
Features
- Altera Stratix IV GX FPGA (EP4SGX230C2/EP4SGX530C2)
- Built-in USB Blaster circuit for programming
- Fast Passive Parallel (FPP) configuration via MAX II CPLD and FLASH
- 6x HSMC connectors (two with transceiver support)
- 2x 40-pin GPIO expansion headers (shares pins with HSMC Port C)
- 2x external PCI Express 2.0 (x4 lane) connectors
- DDR3 SO-DIMM socket (4GB Max), 64MB FLASH, and 2MB SSRAM memory
- 4x LEDs, 4x push-buttons, and 4x slide switches general user I/O
- Onboard 50MHz oscillator and 3x onboard programmable PLL timing chips clock system
- Temperature sensor
- FPGA cooling fan
Specifications
- EP4SGX230:
- 228,000 Logic Elements (LEs)
- 17,133K total memory Kbits
- 1,288 18x18-bit multipliers blocks
- Two PCI Express hard IP blocks
- 744 user I/Os
- Eight Phase-Locked Loops (PLLs)
- EP4SGX530:
- 531,200 Logic Elements (LEs)
- 27,376K total memory Kbits
- 1,024 18x18-bit multipliers blocks
- Four PCI Express hard IP Blocks
- 744 user I/Os
- Eight Phase-Locked Loops (PLLs)
Block Diagram
TR4 Development Board Overview
Videos
Related Product
Altera Stratix® IV High Density High Performance FPGAs
Delivers a breakthrough level of system bandwidth and power efficiency for high-end applications.