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ISSI DDR2 SDRAM

ISSI DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. ISSI DDR2 SDRAM has on-die termination (ODT) and programmable burst lengths of 4 or 8. The on-chip DLL aligns DQ and DQs transitions with CK transitions. 

Features

  • 1GB
    • Clock frequency up to 400MHz
    • 8 internal banks for concurrent operation
    • 4-bit prefetch architecture
    • Automatic and controlled precharge command
    • Power-down mode 
    • Auto-refresh and self-refresh
    • tRAS lockout supported
  • 256Mb & 512Mb
    • JEDEC standard 1.8V I/O (SSTL_18-compatible)
    • Double data rate interface: two data transfers per clock cycle
    • Differential data strobe (DQS, DQS)
    • 4-bit prefetch architecture
    • On-chip DLL aligns DQ and DQS transitions with CK
    • 4 internal banks for concurrent operation

512Mb Functional Block Diagram

Block Diagram - ISSI DDR2 SDRAM

Datasheets

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게시일: 2014-08-21 | 갱신일: 2024-03-05