SW-ONE-QUARTUS

Name: Altera SW-ONE-QUARTUS
Brand: Altera
SKU: 989-SW-ONE-QUARTUS
Price: 5321700 KRW
Availability: OutOfStock

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Mouser 번호:

989-SW-ONE-QUARTUS

제조업체 번호:

SW-ONE-QUARTUS

제조업체:

Altera

설명:

개발 소프트웨어 Quartus Prime Software

데이터시트:

SW-ONE-QUARTUS 데이터시트

추가 정보

Altera SW-ONE-QUARTUS에 대해 자세히 알아보십시오.

구매 가능 정보

재고:: 소프트웨어 라이센스 키는 이메일을 통해 제공됩니다.

수량 입력:

최소: 1 배수: 1

단가:

₩-

합계:

₩-

예상 관세:

본 제품의 배송비는 무료

가격 (KRW)

수량	단가	합계
	₩5,321,700	₩5,321,700

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제품 속성	속성 값	속성 선택
제조업체:	Altera
제품 카테고리:	개발 소프트웨어
RoHS:
브랜드:	Altera
제품 유형:	Development Software
시리즈:	Quartus
팩토리 팩 수량:	1
하위 범주:	Embedded Solutions

제품을 찾음:

유사 제품을 표시하려면 확인란을 하나 이상 선택하십시오.

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속성 선택됨: 0

문서 필터:

데이터시트

SW-ONE-QUARTUS 데이터시트

KRHTS:: 9999999999
CAHTS:: 9999999999
USHTS:: 9999999999
JPHTS:: 999999999
TARIC:: 9999999999
MXHTS:: 9999999999
BRHTS:: 99999999
ECCN:: EAR99

SoC FPGA Family

Altera SoC FPGAs integrate an Arm-based hard processor system (HPS) consisting of processors, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. The devices combine the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic. These user-customizable Arm-based SoC FPGAs are ideal for reducing system power, cost, and board size by integrating discrete processors and digital signal processing (DSP) functions into a single FPGA. They differentiate the end product with custom hardware and software and add support for virtually any interface standard or protocol in the FPGA.

Quartus® Prime Design Software

Altera Quartus^® Prime Design Software delivers improvements across the three key areas designers care about most performance, productivity, and usability. It supports the latest Agilex™ 7 and Agilex 5 FPGA and SoC families, ensuring a seamless development experience for cutting-edge applications. Coming in an upcoming release, support for the new Agilex 3 FPGAs and SoCs family and new MAX 10 FPGA package options that squeeze 485 I/Os into a 19 x 19mm² sized package. Fast compile times allow designers to accelerate FPGA development, with larger designs benefiting from even greater reductions. Enhanced compiler optimizations also significantly reduce peak virtual memory requirements, ensuring most FPGA designs compile within 64GB of memory.