Analog Devices Inc. AD9528 JESD204B 클럭 생성기
LVDS/HSTL 출력부가 14개 있는 Analog Devices AD9528 JESD204B 클럭 생성기는 여러 소자의 동기화를 위한 JESD204B SYSREF 생생기가 내장된 2단 PLL(위상 고정 루프)를 갖추고 있습니다. 첫 번째 단(PLL1)은 시스템 클럭 상의 지터를 줄여 입력 기준 조정 기능을 제공합니다. AD9528의 제2단 PLL(PLL2)은 고주파 클럭을 포함합니다. 이런 고주파 클럭은 클럭 출력 드라이버에서의 낮은 통합 지터와 낮은 광대역 잡음을 보장합니다. 외부 VCXO는 허용 가능한 성능에 필수적인 제한적 위상 잡음 및 지터 요건을 갖추도록 PLL2에서 필요한 저잡음 기준을 제공합니다. AD9528의 온칩 VCO는 3.45~4.025GHz 범위에서 조절됩니다. 통합형 SYSREF 생성기는 PLL1 및 PLL2 출력에 동기화된 싱글 샷, N 샷 또는 연속 신호를 출력하여 여러 소자의 시간을 동기화합니다. AD9528 JESD204B 클록 생성기는 고성능 무선 송수신기, LTE 및 다중 반송파 GSM 기지국, 무선 및 광대역 인프라, 의료 및 고성능 계측 장치에 매우 적합합니다.
The first stage (PLL1) offers input reference conditioning by decreasing the jitter on a system clock. AD9528’s second stage PLL (PLL2) includes high-frequency clocks. These high-frequency clocks ensure low integrated jitter and low broadband noise from the clock output drivers. The external VCXO provides the low-noise reference required by PLL2 to have the restrictive phase noise and jitter requirements necessary for acceptable performance. AD9528’s on-chip VCO tunes from 3.45GHz to 4.025GHz. The integrated SYSREF generator outputs single shot, N-shot, or continuous signals synchronous to the PLL1 and PLL2 outputs to time-align multiple devices.
The AD9528 JESD204B Clock Generators generate two outputs (Output 1 and Output 2) with a maximum frequency of 1.25GHz, and 12 outputs up to 1GHz. Designers can configure each output to link directly from PLL1, PLL2, or the internal SYSREF generator. AD9528’s 14 output channels include a divider with coarse digital phase adjustment and an analog fine phase delay block. This allows complete flexibility in timing alignment across all 14 outputs.
Designers can use the AD9528 as a dual-input flexible buffer to distribute 14 device clock and/or SYSREF signals. At power-up, the AD9528 sends the VCXO signal directly to Output 12 and Output 13 to serve as the power-up ready clocks.
특징
- 14 outputs configurable for HSTL or LVDS
- Maximum output frequency
- 2 outputs up to 1.25GHz
- 12 outputs up to 1GHz
- Dependent on the voltage-controlled crystal oscillator
- (VCXO) frequency accuracy (start-up frequency accuracy: <±100ppm)
- Dedicated 8-bit dividers on each output
- Coarse delay: 63 steps at 1/2 the period of the RF VCO divider output frequency with no jitter impact
- Fine delay: 15 steps of 31ps resolution
- Typical output to output skew: 20ps
- Duty cycle correction for odd divider settings
- Output 12 and Output 13, VCXO output at power-up
- Absolute output jitter: <160fs at 122.88MHz, 12kHz to 20MHz integration range
- Digital frequency locks detect
- SPI- and I²C-compatible serial control port
- Dual PLL architecture
- PLL1
- Provides reference input clock clean up with external VCXO
- Phase detector rate up to 110MHz
- Redundant reference inputs
- Automatic and manual reference switchover modesRevertive and nonrevertive switching
- Loss of reference detection with holdover mode
- Low noise LVDS/HSTL outputs from VCXO used for radio frequency/intermediate frequency (RF/IF) synthesizers
- PLL2
- Phase detector rate of up to 275MHz
- Integrated low noise VCO
애플리케이션
- High-performance wireless transceivers
- LTE and multi-carrier GSM base stations
- Wireless and broadband infrastructure
- Medical instrumentation
- Clocking high-speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs; supports JESD204B
- Low jitter, low phase noise clock distribution
- ATE and high-performance instrumentation
Block Diagram
